KEYNOTE SPEAKERS
REGINA DITTMANN
Regina Dittmann
Regina Dittmann is Director of the Peter Grünberg Institute 7 at Forschungszentrum Jülich, one of the pioneering groups in memristive devices and their application in RRAM and neuromorphic circuits. She is internationally recognized for her expertise in the growth of oxide thin films and in elucidating the operating and failure mechanisms of memristive devices.
She received her degree in Physics from the University of Cologne in 1990 and her PhD in Physics from the University of Giessen in 1994. In 2001, she was awarded a Young Investigator Group grant at Forschungszentrum Jülich, followed by a W2/W3 grant from the Helmholtz Association in 2011. Since November 2012, she has also been a Professor at the Faculty of Electrical Engineering and Information Technology at RWTH Aachen University. In 2022, she was appointed Lise Meitner Guest Professor at the Faculty of Engineering at Lund University, Sweden.
Regina Dittmann has co-authored more than 300 scientific publications. Her seminal paper on redox-based resistive switching and nanoionic mechanisms has been cited over 6,000 times. She has served as coordinator and principal investigator in numerous national and international projects, including as co-speaker of the Collaborative Research Centre SFB “Nanoswitches,” funded by the German Research Foundation. Since 2025, she has been coordinating the NEURTEC project, a joint initiative about memristor-based neuromorphic computing between RWTH Aachen University and Research Centre Jülich.
Wednesday 9 September
08:30 - 09:10
Sala Magna
Chair:
Memristive crossbar arrays based on valence change mechanism (VCM) resistive random-access memory (RRAM) are considered a promising solution to overcome the latency and energy limitations of von Neumann architectures for neural network training and inference. In this talk, we present a comprehensive study of VCM-based devices and 1T1R arrays, addressing key challenges in reliability, linear programming, multilevel operation, and circuit-level integration. We demonstrate their capability for in-memory vector–matrix multiplication, and demonstrate novel pathways for spatio-temporal processing for bio-inspired computing.
Precise control of intermediate conductance states is essential for multi-bit storage and synaptic weight representation. We demonstrate that both pulse amplitude and timing enable controlled modulation of the conductance window, allowing stable multilevel programming. The coupling between electrical excitation and thermal dynamics introduces temperature as an additional state variable, enabling the coexistence of long-term potentiation (LTP) and short-term plasticity (STP), and thus supporting dynamic, history-dependent learning functionalities.
Analog neuromorphic computing requires gradual and linear conductance updates. However, filamentary VCM devices typically exhibit abrupt SET transitions due to electrothermal feedback. By applying sub-100 ps voltage pulses to Pt/TaOx/Ta/Pt devices, we suppress this feedback and achieve highly linear potentiation (R² = 99.5% over more than 100 pulses). Using advanced measurement techniques enabling conductance extraction down to 50 ps, we further show that reducing pulse delays below ~250 ps leads to thermal accumulation. This results in frequency-dependent potentiation, where switching dynamics accelerate and linearity can be tuned via pulse timing.
The performance of 1T1R cells is governed by the interaction between the nonlinear RRAM device and the access transistor. Crossbar arrays co-integrated with CMOS were investigated for different transistor geometries, providing design guidelines for resistance window control and application compatibility. Functional validation through vector–matrix multiplication confirms their suitability for in-memory computing, while negligible cell-to-cell interference supports scalability. A method to extract intrinsic I–V characteristics of the RRAM cell from 1T1R measurements is introduced, enabling detailed analysis of voltage drops across both elements. The results show that the operating point of the voltage divider can be tuned between linear and saturation regimes of the transistor, strongly influencing switching kinetics. Trade-offs arise between low-current SET and high-current RESET requirements; as a potential solution, a 2T1R architecture combining high- and low-drive transistors is proposed to decouple these constraints.
In summary, this work provides a unified understanding of VCM-based memristive devices across device, circuit, and array levels, establishing key design guidelines for reliable, linear, and multilevel operation toward scalable neuromorphic hardware.